1. Field of the Invention
The present invention relates to enhancement of the edges of an electrical signal. More particularly, the present invention relates to a circuit and method for detecting an edge of a digital signal, and driving the next state of the signal based on the detected signal edge to reduce the rise and fall time of the signal.
2. Description of the Related Art
Many factors in today's complicated integrated circuits (ICs) limit their maximum operational speed. For instance, ICs typically have long, interconnected electrical wiring inherently exhibiting significant delays from rise and fall times based on the resistance and capacitance of the electrical wiring. This delay is conventionally known as a time constant, and is calculated by the equation T=RC, where T is time in seconds, R is resistance in ohms, and C is capacitance in farads.
All electrical wiring in ICs has some amount of resistance and some amount of capacitance, although it is generally minimized by designing ICs with the shortest possible routes and maximum isolation from other wiring. Nevertheless, the edges of digital signals have exponentially rising and falling edges. Consequently, the resistance and capacitance in the electrical wiring inside ICs leads directly to significant propagation delays.
FIG. 10A depicts a wiring path 36 in an IC exhibiting propagation delay because of its resistance and capacitance. One conventional solution to improve excessive propagation delay is to place buffers 32 and 34 in series along the wiring route 36a, 36b, as shown in FIG. 10B. In FIG. 10B, an otherwise long wiring route is broken into two parts 36a and 36b, and two inverters forming buffers 32 and 34 are placed serially there between. The breaking of the electrical wiring route 36 as shown in FIG. 10A into two parts 36a, 36b as shown in FIG. 10B increases the overall delay of the signal because a signal must propagate through active buffer components, e.g., at least two metal oxide semiconductor field effect transistors (MOSFETs) 600n, 600p as shown in FIG. 10B. Moreover, because the wiring route 36 is physically cut into two parts 36a, 36b (FIG.10B), a contact resistance is added to the circuit because of contacts with the cut portions. These and other factors increase propagation delays even further.
Thus, there is a need to improve the propagation delays in an electrical wiring route of an IC without adding further delays to the overall device speed.